The present invention generally relates to a bit slice data path design and more specifically to techniques for synchronizing signals that cross two different time domains for chips in a bit slice data path design.
The bit slice data path design includes multiple chips that are coupled to a common data bus. The multiple chips are used to process a slice of data for the data bus. Multiple chips are used to operate on a large data bus that is too wide to fit into a single chip because a single chip cannot handle the processing of data for the entire data bus.
Each of the multiple chips process data on the same clock-for-clock cycle. A problem is introduced if the data has to synchronously cross a time domain across all data slices. For example, a first time domain operating in a first frequency may send a signal to a second time domain operating in a second frequency. In order for the first time domain to communicate with the second time domain, the signal is sent through a synchronization circuit that synchronizes the signal in the first frequency to a signal in the second frequency. A problem is introduced because the signal should cross from the first time domain to the second time domain in all slices at the same time. If the signal does not cross a time domain in all chip slices at the same time, data corruption may result.
When a signal is sent from the first time domain to the second time domain in all chip slices of the bit slice design, the signals may not be received at the second time domain in the same clock period for all the chips. Various factors may occur to cause signals to cross the time domains at different clock periods. For example, the time to synchronize the signal may vary among the chips. For example, a synchronization circuit of a first chip may take two clock cycles and a synchronization circuit of a second chip may take three clock cycles to synchronize the signal. Thus, the signal may arrive at the second time domain for the two chips at different times. Then, the two chips may not be processing data on the same clock cycle, which may result in errors.
Accordingly, techniques for synchronizing a signal from a first time domain to a second time domain across multiple chips in a bit slice design are desired.